The present invention relates to a method and/or architecture for implementing a phase lock loop generally and, more particularly, to a method and/or architecture for implementing a zero phase and frequency restart phase lock loop.
An acquisition of an input signal by a conventional phase lock loop (PLL) commonly involves three phases or modes. First, a single cycle zero phase start (ZPS) is performed to initialize a PLL clock signal phase at approximately an input signal phase. A short PLL phase-only mode is then performed to minimize any error in the PLL clock signal phase relative to the input signal phase. Finally, a phase and frequency acquisition mode is entered where the PLL clock tracks the input signal in both phase and frequency. The conventional acquisition approaches are limited in that convergence to the correct phase and frequency takes a considerable amount of time.
A common method of improving the acquisition speed of a PLL is to change a loop bandwidth of the PLL, known as gear shifting, when changing modes. A high loop bandwidth (i.e., Gear 1 mode) is used during the phase-only mode to adjust the PLL clock signal phase rapidly. A low loop bandwidth (i.e., Gear 2 mode) is used during the phase and frequency acquisition mode and while tracking data to reduce an output jitter.
Referring to FIG. 1, a waveform of a signal 20 from a conventional disk drive sector with no noise is shown. The signal 20 consists of three parts, a preamble 22, a sync mark 24, and data 26. FIG. 2 is a waveform of a signal 28 similar to signal 20 with typical noise added. The signal 28 includes the preamble 22, the sync mark 24, and the data 26. The preamble 22 is commonly made up of a repeating 2Txe2x80x942T signal. Because of the high density at which the signal 28 is recorded, the preamble 22 is virtually a sine wave.
In a conventional hard disk drive application, the preamble 22 and sync mark 24 appear at the start of each sector of data 26. As a result, a PLL reading the signal 28 must reacquire phase lock at the start of each sector. The ZPS PLL determines the phase from a single cycle of the preamble 22. The Gear 1 and The Gear 2 modes are continuously using the most recent phase data and discarding older data (low pass filtering). If the phase lock acquisition time of a PLL can be shortened, then the preamble 22 in each sector can be made smaller. Smaller preambles 22 leave more room in the disk for the data 26.
The present invention concerns a circuit generally comprising a first circuit and a phase lock loop. The first circuit may be configured to (i) collect a plurality of samples per cycle during a plurality of cycles of an input signal and (ii) calculate a phase offset and a frequency offset for the input signal relative to a clock signal in response to the samples. The phase lock loop may be configured to (i) preset a phase error signal to the phase offset and a frequency error signal to the frequency offset and (ii) generate the clock signal in response to the phase error signal and the frequency error signal.
The objects, features and advantages of the present invention include providing a phase lock loop that may (i) lock to an input signal in a short time, (ii) lock to an input signal with a small frequency and phase starting error, and/or (iii) quickly lock to an input signal having a known frequency preamble.